This invention relates generally to a digital system in which a high speed clock signal and a frame synchronization signal are needed at one or more locations/components remote from the origination location of the signals.
A high speed data or communication system requires time alignment to a master clock. Systems that employ multiple high speed digital processors often require synchronization with each other in order to properly process incoming data. The distribution of the clocks to the various points of use requires attention to the time alignment of high speed master clocks relative to lower speed synchronization clocks in order to maintain setup and hold time margins for transferring data. The time alignment is impaired by variations in time delay on the separate paths taken by one clock versus another. High bandwidth circuits and transmission media can help to improve alignment accuracy but come with disadvantages such as increased size, weight, power, and cost.
Generation and distribution of a sinusoidal multi GHz reference clock, with equivalent rise time of tens of picoseconds, to all elements in a processor with precise phase alignment can be achieved using passive power splitters and coaxial cables with controlled lengths. The bandwidth of a sinusoidal reference clock distribution system can be very low and therefore clock jitter due to integrated phase noise and deterministic jitter is limited.
However, the distribution of a low frequency frame sync signal to all elements in a multi-element system with its critical timing edges precisely aligned to the high speed master reference clock presents significant challenges, e.g. requiring sufficient setup and hold times to permit re-clocking by the reference clock to remove any phase jitter and timing error. For example, a system timing budget with a 10 GHz reference clock with a clock period T of 100 ps would typically (for integrated circuits using 25 nm CMOS or InP) require 10 ps each for setup and hold times (10%+10%) in order to reclock the frame synchronization signal. Subtracting 30 ps for rise and fall times (30%), and an addition 10 ps for jitter (10%), from the 100 ps clock period leaves only 40 ps (40%) for total timing skew between the 10 GHz reference clock and the synchronization signal at the destination where reclocking occurs. In order to achieve error-free transmission of system data this timing uncertainty needs to be in practice sufficiently less than 40% (e.g., 20% or 20 ps.). To avoid signal distortion that would be perceived as a timing error the distribution system for the frame synchronization signal, e.g. at 10 MHz, must be sufficiently broadband to accommodate all of the harmonics arising from the digital signal's rise and fall times; in this case 30 ps, which is roughly equivalent to the 10 GHz reference clock. Practical coaxial and twisted shielded pair cable media, connectors, and printed circuit board traces result in substantial high frequency attenuation at the 10 GHz equivalent band edge, relative to 10 MHz, and therefore introduce signal distortion and group delay errors in the frame sync signal. Employing an equalization circuit may partially offset the synchronization signal distortion due to high frequency attenuation provided overall attenuation is not excessive. However the ability to distribute a synchronization signal that is group delay-matched to the reference frequency, in this example 20 ps, is limited to short distances and is impractical without costly low loss interconnecting media, matching equalization, and, of course, careful matching of the nominal path lengths and their associated delays. Furthermore, clock distribution systems often employ AC coupling to eliminate DC offset problems and it is difficult to obtain broadband AC coupling and DC restoration (Bias-T) components that support a large ratio of upper frequency limit to the AC coupling frequency (which must be on the order of 50 times lower in frequency than the synchronization frequency in order to control “droop”). Thus, there exists a need for an improvement in the distribution of frame sync signals with a high speed master clock signal where the frame sync signal is relatively low in frequency relative to the frequency of the master clock.